Charge based DC compact modeling of bulk FinFET transistor

Abstract

Multiple-gate MOSFETs became an industrial reality in the last years. Due to a pragmatic trade-off between CMOS process baselines compatibility, improved performance compared to planar bulk architecture, and cost, bulk FinFETs emerged as the technological solution to provide downscaling for the 14/22nm technological nodes. In this work, a charge based DC compact model based on the SDDG Model is demonstrated for this new generation of FinFET transistors and describes continuously the transistor characteristics in all operating regions. Validating the model against two bulk FinFET baselines (NMOS, PMOS, various gate lengths and EOT), an excellent agreement is found for transfer and output characteristics (linear and saturation regimes), transconductance/output conductance, and gm/IDS characteristics. Temperature dependence is also taken into account and validated (T range from 25°C up to 175°C).