Characterizing SRAM and FF soft error rates with measurement and simulation

Abstract

Soft error originating from cosmic ray is a serious concern for reliability demanding applications, such as autonomous driving, supercomputer, and public transportation system. Also, as the number of electronic devices increases, consumer electronics may require higher reliability than ever. On the other hand, device miniaturization and lower voltage operation degrade the immunity of SRAM and flip-flops in VLSI, and then soft error countermeasures will be demanded in more and more products. This paper characterizes and discusses soft error rates of SRAM and flip-flops in the terrestrial environment. Measured soft error rates of bulk and FDSOI SRAMs are presented. Also, the multiplicity and mechanism of multiple cell upsets (MCUs), which can spoil error correction code (ECC), are discussed. Flip-flops are also sensitive to radiation, but its protection is not well established since ECC cannot be applied. This paper reviews redundant FFs that are developed aiming at higher radiation immunity and demonstrates the resilience improvement with irradiation test results. Also, the importance of layout design is pointed out with a comparative study. Simulation, on the other hand, is a key technology to understand the soft error mechanism and guide radiation aware design for higher reliability. This paper outlines a physics-based multi-scale Monte Carlo simulation framework tailored for soft error simulation. The simulation flow and the model construction are explained, and some important implications are derived from the simulation results that assume 65-nm to 25-nm SRAMs. Finally, this article touches on future trends regarding device structure and overlooked secondary cosmic rays. The advantage and unique features of FinFET recently reported in literature are introduced. Also, muon-induced soft error is discussed focusing on the difference between positive and negative muons.