Abstract
In this paper, we present a new process flow to increase cell capacitance in planar dynamic random access memory cells designed for system-on-chip applications. Silicon dioxide of shallow trench isolation (STI) under capacitor electrodes is recessed to increase cell capacitance. It appears that the cell capacitance is increased to 25% when the STI recess is 0.15 μm. The recession slightly decreases junction leakage current due to annealing of defects and also relief of STI stress. These combined effects increase refresh time about 50% in 1 Mb memory array. The distribution of breakdown voltage in capacitor oxide shows similar behavior compared with samples without STI recessed. Also, the lifetime of the capacitor oxide evaluated from the Weibull method exceeds 2000 years. © 2004 The Electrochemical Society. All rights reserved.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
