Characterization of the VMM front-end ASIC for High-Resolution Applications

Abstract

The VMM is a high-functionality front-end Application-Specific Integrated Circuit (ASIC) designed to readout particle tracking detectors. As a front-end device, it allows for processing of radiation-induced pulses, via its 64 independent channels, which perform charge amplification, shaping, and pulse amplitude and timing measurements that may be digitized by embedded moderate-resolution 10- and 8-bit converters. The results are stored in internal buffers, in order to be extracted by an independent readout device. The pulse is fully processed by a channel within a few hundred nanoseconds. This short deadtime, makes the VMM ideal for high-rate applications, such as the Toroidal LHC Apparatus (ATLAS) experiment of the Large Hadron Collider (LHC), which will employ it in one of its major overhauls, the New Small Wheel (NSW) upgrade. However, due to the flexibility of its analog front-end circuitry, the VMM may also be used in other implementations, which may favor a more precise pulse amplitude and timing estimation over processing speed. In this work, the VMM's legacy readout mode will be demonstrated, in which the ASIC's ADCs are bypassed, and an external digitizer is used to sample the analog information instead. The ASIC is configured and read-out via an FPGA, which utilizes its embedded 12-bit ADC to sample the VMM's analog outputs. Besides a description of the front-end FPGA firmware's functionalities, this study also provides an overview of a multiple-FPGA data acquisition scheme, which was designed in such a way as to minimize digital interference to the VMM's analog front-end circuitry.