Abstract
The upgrades of the Large Hadron Collider (LHC) at CERN and the experiments in 2019-20 (LS2) and 2024-26 (LS3) will allow to increase the instantaneous luminosity. During LS2, each of the so-called Wheels of the ATLAS muon spectrometer are planned to be replaced by the New Small Wheel (NSW), which will be comprised of two gaseous detector technologies, namely the Micromegas (MM), mainly used for track reconstruction and the small strip Thin Gap Chambers (sTGC), mainly used for triggering. The $2.4$ million readout channels of those chambers will require a new generation of electronics to read them out, that will be able to endure a harsh radiation environment while at the same time be compatible with the Phase-II trigger rates, which are expected to reach a Level-0 frequency of $1 \, \mathrm{MHz}$ and a Level-1 frequency of $400 \, \mathrm{kHz}$. Several custom Application-Specific-Integrated-Circuits (ASICs) have been developed for the electronics system of the NSW, besides special boards to house these ASICs, as well as dedicated Field-Programmable Gate Array (FPGA) designs. A general overview of the main elements of the NSW electronics scheme is provided here.
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