Characterization of mixed-signal properties of MOSFETs with high-k (SiON/HfSiON/TaN) gate stacks

Abstract

The correlation between the stoichiometry of HfSiON gate dielectrics and mixed-signal properties of low-power MOSFETs is investigated. MOSFETs with gate length L down to 100 nm were fabricated in a conventional fabrication flow with a thermal budget of 1000/spl deg/C. The equivalent oxide thickness values of the gate stacks ranged from 12.0 to 14.4 /spl Aring/. The inversion thickness t/sub ox//sup inv/ ranged between 16.2 and 18.9 /spl Aring/. Accumulation leakage current density at V/sub g/=V/sub fb/-1 V ranged from 3.1/spl times/10/sup -3/ to 3.9/spl times/10/sup -2/ A/spl middot/cm/sup -2/, corresponding to a leakage reduction of around 1000 times compared with that of SiON/TaN. The inversion leakage current density at V/sub g/=V/sub t/+0.7 V was found to be between 0.18 and 0.66 A/spl middot/cm/sup -2/, i.e., 20 times lower than that of SiON/TaN. The threshold voltage instability (/spl Delta/V/sub t/) of the high-k gate stacks was found to be below 10 mV, corresponding to a (bulk) oxide trap density N/sub ot/<3/spl times/10/sup 10/ cm/sup -2/. Normalized input-referred gate noise spectra S/sub vg/ showed minor dependence on the Hf content of the gate dielectric. This is attributed to the fact that the main sources for the low-frequency (LF) 1/f noise are defects located at the interfaces rather than bulk defects in the gate dielectric. Moderate high- and low-field mobilities of 50%-70% of a SiON/TaN reference device were found in MOSFETs with Hf-based gate dielectric. Of the investigated layers, stoichiometric (55% Hf) and Hf-rich (70% Hf) silicates on SiO/sub 2/ interface show the best compromise in terms of gate leakage reduction, threshold voltage instability, LF noise, drive current, and analog voltage gain. For an HfSiON silicate dielectric layer with 70% Hf and SiO/sub 2/ interface, a low-field peak electron mobility /spl mu//sub eff/=148 cm/sup 2//V/spl middot/s, an oxide trap density N/sub ot/<1.4/spl times/10/sup 10/ cm/sup -2/, and a drive current I/sub ON/=459 /spl mu/A//spl mu/m at I/sub OFF/=9 pA//spl mu/m were found. The analog voltage gain A/sub v/ of a MOSFET with this gate dielectric and W/L=1/0.45 was found to be A/sub v/=121. To meet specifications for mixed-signal properties, optimization of dopant engineering along with tuning of the gate stack properties is required to improve the performance of high-k-based MOSFETs.