Characterization of interface state density of three-dimensional Si nanostructure by charge pumping measurement

Abstract

Adopting the gated p–i–n diode configuration, the interface state density (Dit) at the Si/SiO2 interface of Si fin structures on Silicon-on-Insulator (SOI) wafers has been systematically studied using charge pumping method. The optimal forming gas annealing temperature for the three-dimensional (3D) surface is extracted. A new methodology for separately quantifying the local Dit at different regions of the 3D surfaces (i.e., the top/side walls and the corners) is also derived by characterizing the fins with various widths and the planar counterparts. The results validate the necessity to independently consider the corner regions, at which substantially high local Dit situates, and thus further clarify the origin of high Dit at 3D surfaces.