Characterization of in-process substrate warpage of underfilled flip chip assembly

Abstract

In the flip chip on board assembly process, the CTE mismatch among the materials inevitably causes substrate warpage. The substrate warpage introduces undesired residual stresses in the silicon chip and underfill materials. Detrimental residual stresses reduce the reliability of flip chip systems. Severe warpage of a substrate after the flip chip assembly process may lead to fracture of solder joints, underfill delamination or underfill cracks. In this research, an experimental approach is developed to investigate the assembly process-induced stresses in flip chip assembly as well as the associated substrate warpage. Flip chip test vehicles with build-in piezoresistive stress sensors are utilized to quantitatively characterize the residual stresses on silicon flip chips during the assembly process. The in-process substrate warpage is measured by a shadow moire system. The characteristics of process-induced stresses in flip chip systems and substrate warpage are discussed in detail in this paper.