Abstract
Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.
Highlights
The aggressive scaling of the equivalent oxide thickness (EOT) of metal–oxide–semiconductor field-effect transistors (MOSFETs) for achieving sophisticated device speeds and minimal power consumption has made SiO2 obsolete as an insulating material [1,2,3]
For the formation of metal–oxide–semiconductor capacitors (MOSCAPs), a 5 nm TiN metal layer was deposited by atomic layer deposition (ALD) on top of the Al2 O3 dielectric film in all cases, which followed by deposition of a Ti/Au
From the inversion responses obtained in the three cases, it is evident that the sample deposited at 300 ◦ C has the lowest leakage current; it has the lowest dispersion in the accumulation region, as depicted in Figure 1a, which indicates a lower density of border traps
Summary
The aggressive scaling of the equivalent oxide thickness (EOT) of metal–oxide–semiconductor field-effect transistors (MOSFETs) for achieving sophisticated device speeds and minimal power consumption has made SiO2 obsolete as an insulating material [1,2,3]. These traps are commonly known as border traps, which are an inherent property of oxides [13,14,15] Because of this above-explained alignment of the Fermi level with the energy band of border traps, these traps capture or release the channel electrons via tunneling. This carrier exchange time is governed mainly by the applied. Both of these kinds of electrical traps (border and interface traps) are characterized by varying two ALD conditions: the deposition temperature and the purge time. The stress responses of the films under constant voltage are examined
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