Abstract
In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5 nm. We show that this phenomenon is accentuated in high stress accumulation V g=?3 V, V d=3 V, but more less for stress V g=V d=3 V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.
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