Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

C Chen,L Xiao,P Moreira,D Gong,J Prinzie,T Liu,Q Sun,P Wang,J Ye,S Kulis,G Huang,X Huang,P Leroux,D Guo,C Liu

doi:10.1088/1748-0221/15/03/t03005

Abstract

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

Highlights

The input signals of the upstream channels of GBCR come from the aggregator with an output amplitude of larger than 200 mV
The output amplitude of the upstream channels of GBCR must be larger than 400 mV
We have designed and tested a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC) called GBCR fabricated in a 65-nm CMOS technology for the ATLAS Inner Tracker (ITk) detector readout upgrade

Summary

Input stage

When a high-speed signal passes through a long cable, its high-frequency components attenuate more than its low-frequency components, resulting in the signal quality deterioration. We adjust the equalization strength by tuning Cs and Rs, based on the high-frequency loss of the long cable and the data rate. The overall bandwidth of LAs is 3.3 GHz. Figure 5 is the block diagram of the CDR module and the AFC module. The PD detects the phase difference between the 5.12GHz clock from the VCO and the 5.12-Gbps data from the equalizers. The VCO adjusts its output frequency to follow the frequency of the input data until the two phases are close. GHz. The AFC module ensures the output frequency of the VCO to be close to 5.12 GHz by one of these two 40 MHz clocks

CML driver

Downstream Channel

Upstream channels

Downstream channel

Irradiation tests

Summary and outlook