Abstract
ABSTRACTElectrical and crystal properties of seeded lateral epitaxial Si are evaluated as a function of distance from seeding area with the aid of a micro-probe RHEED and MOSFET fabrication. the results indicate that the quality of a grown layer is as good as that of bulk Si Crystal for most of the epitaxial layer. However, at the SiO2 edge, electrial properties are somewhat poor due to the existence of dislocation and residual stress.Element devices useful for SO structures are fabricated. Electrical properties of MOSPET's with double active areas indicate that surface and bottomregions of the epitaxial layer are all of device worthy quality.Insulated control gate bipolar type transistors are proposed and some preliminary results are shown.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
