Abstract
A report is presented on the fabrication and characterisation of a vertical interconnection substrate which uses silicon vias surrounded by glass in an effort to solve existing problems with the conventional method, i.e. voids in the via, cracking during a high-temperature process, and isolation failure between the via and the substrate. The silicon via and integrated glass are fabricated by means of DRIE with silicon and a glass-reflow process, respectively. The fabrication results demonstrated that the silicon via is void-free and perfectly isolated. The resistance of the via was measured to be 91.9 mΩ on average with 23.4 mΩ standard deviation. The substrate is expected to be applied to electrical interconnection of electrostatically actuated devices as well as to micro-device packaging at the wafer level.
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