Abstract
This chapter discusses the design of switched-capacitor (SC) delta-sigma (∆Σ) modulators appropriate for multi-standard radio-frequency (RF) receivers. It provides an overview of different RF receiver architectures and presents the top-down design of a pair of quadrature complex third-order ∆Σ modulators for a low-power multistandard RF transceiver. The design of the RF transceiver targets the performance suitable to support three wireless communications standards: global system for mobile communications (GSM), wideband code division multiple access (WCDMA) and digital enhanced cordless telecommunications (DECT). It has been demonstrated that the high-frequency IF signal digitization can be performed by a pair of low-pass ∆Σ modulators. The chapter describes the system-level design of the ∆Σ modulators. The results of computer-based behavioral simulations have also been presented. The chapter describes the circuit implementation of ∆Σ modulators, and presents the measurement results. It illustrates the ideal noise transfer functions (NTF) for the GSM and the WCDMA standards. It closes by summarizing the performance of the ∆Σ modulators.
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