Chapter 7 - Interconnects

Abstract

This chapter discusses the interconnection system of the 25xxx and 26xxx parts as well as the new systems of Programmable System-on-Chip (PSoC) families. The digital interconnects for the 25xxx/26xxx series have two general inputs to the digital blocks: the logic input and the clock input. The global buses are represented in two columns around the digital blocks. There is a label at the top of the columns depicting the organization of the buses. The comparator bus is an interconnect that is available only to the logic input of the digital block. Certain analog modules have the ability to connect to the comparator bus and thereby provide a digital signal to the digital blocks. The analog blocks have input signals and clocking signals. The clocking signals are routed to the multiplexers on the top left of each column of the analog blocks. These multiplexers are used to select the clock signal for the entire column. The multiplexer can choose the clock from one of four sources—24V1, 24V2, AnalogClock_0_Select, or AnalogClock_1 Select.