Abstract
Multiprocessor systems-on-chips (MPSoCs) show complex run-time behavior due to the implementation of multiple hardware, software, and communication scheduling strategies in one system. This chapter focuses on the verification aspect of MPSoC—function verification and target architecture performance verification. The aim is to provide an understanding of the target architecture run-time effects and to review more efficient and reliable alternatives to cosimulation based performance verification based on formal performance analysis. Formal software performance analysis differentiates two problems—formal process performance analysis and schedulability analysis. The first one analyzes the execution time of a process running on a single processor without resource sharing, and the second one analyzes the effects of resource sharing on one or multiple processors. The chapter also reviews architecture component modeling and analysis techniques. It also introduces resource sharing including standard scheduling and performance analysis approaches. The results are the execution time and the communication volume of a process, or the timing of a communication element.
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