Chapter 5 - Programming (Configuring) an FPGA

Abstract

This chapter discusses the detailed mechanisms for programming field programmable gate arrays (FPGAs) that vary on a family-by-family basis. It describes a variety of tools and flows that are used to capture and implement FPGA designs. The result of all of these techniques is a configuration file that contains the information that will be uploaded into the FPGA in order to program it to perform a specific function. In the case of static random-access memory (SRAM) based FPGAs, the configuration file contains a mixture of configuration data and configuration commands. When the configuration file is in the process of being loaded into the device, the information being transferred is referred to as the configuration bitstream. In the case of antifuse-based FPGAs, the antifuse cells are visualized as scattered across the face of the device at strategic locations. The device is placed in a special device programmer, the configuration (bit) file is uploaded into the device programmer from the host computer, and the device programmer uses this file to guide it in applying pulses of relatively high voltage and current to selected pins to grow each antifuse in turn. In the case of FPGAs containing large blocks of embedded (block) RAM, the cores of these blocks are implemented out of SRAM latches and each of these latches is a configuration cell that forms a part of our “imaginary” register chain.