Chapter 3 - Instruction Formats (I)

Abstract

This chapter presents the instruction set formats of Alpha AXP processor circuit. Each Alpha AXP processor has a set of registers that hold the current processor state. If an Alpha AXP system contains multiple Alpha AXP processors, there are multiple per-processor sets of these registers. The Alpha AXP processor has 32-integer value registers, 32-floating point registers, one program counter (PC). There are five basic Alpha AXP instruction formats: (1) memory, (2) branch, (3) operate, (4) floating-point operate, and (5) PALcode. All instruction formats are 32-bits long with a 6-bit major opcode field in bits <31:26> of the instruction. The Memory format is used to transfer data between registers and memory, to load an effective address, and for subroutine jumps. Memory format instructions with a function code replace the memory displacement field in the memory instruction format with a function code that designates a set of miscellaneous instructions. The operate format is used for instructions that perform integer register to integer register operations. The operate format allows the specification of one destination operand and two source operands. The floating-point operate format is used for instructions that perform floating-point register to floating-point register operations. PALcode format is used to specify extended processor functions. The source and destination operands for PALcode instructions are supplied in fixed registers that are specified in the individual instruction descriptions.