Chapter 29 - Power and Leakage

Abstract

Power dissipation has become a top priority for today's microprocessors. The power dissipated by typical modern circuits can be broken up into three main categories: dynamic or switching power, short circuit power, and leakage power. Leakage power is becoming the dominant source of power dissipation in modern and future circuits. This chapter focuses largely on leakage in memory circuits—in particular, understanding the mechanism and measuring the effects. In the deep submicron regime, as CMOS circuit threshold voltage, channel length, and gate oxide thickness decrease, high leakage current is becoming a significant contributor to power dissipation. Many devices and techniques are proposed to reduce leakage power. These include body-biased transistors, sleep transistors, and dual threshold voltage CMOS designs, which include Multiple Threshold CMOS (MTCMOS), sleep transistors, and domino logic design techniques. Most techniques provide solutions for gate leakage. Increasing threshold voltage, either statically or dynamically, typically optimizes subthreshold leakage current. Cache power dissipation has typically been significant, but the increasing trend of leakage power will have a greater impact on the cache since most of its transistors are inactive (dissipating no dynamic power, only static) during any given access. It is therefore essential to properly account for these leakage effects during the cache design process.