Chapter 23 - Design and Verification Tools

Abstract

There are a multifarious multitude of tools used for the design and verification of electronic systems. In the days before computer-aided design and verification tools, analog design engineers captured their designs as hand-drawn transistor-level schematics. Sometime around the 1970s, folks started to create simple computer-aided tools that could read a text file containing a netlist and perform simple checks, such as checking that transistors were connected the right way. The first such Hardware Description Languages (HDLs) were proprietary; later, the industry adopted standard languages such as Verilog and VHDL. In the not-so-distant past, the term formal verification was considered to be synonymous with equivalency checking for the majority of design engineers. Toward the end of the 1980s, Logic (RTL) Synthesis tools started to appear for use in digital integrated circuit design. The idea here is that the design engineers capture the desired functionality of the system in RTL, and the synthesis program then automatically converts the RTL representation into a corresponding gate-level netlist. In the case of digital designs, the most common form of timing verification in use today is classed as Static Timing Analysis (STA). Statistical Static Timing Analysis (SSTA) is based on generating a probability function for the delay associated with each signal for each segment of a track, then evaluating the total delay probability functions of signals as they propagate through entire paths. A type of program called an Automatic Test Pattern Generator (ATPG) can be used to automatically create tests to check individual integrated circuits or entire circuit boards.