Chapter 20 - Advanced Packaging Techniques

Abstract

In a package containing a single silicon chip (die), the back of the die is attached to the substrate, and an automatic wire-bonding tool connects the pads on the die to corresponding pads on the substrate with wire bonds finer than a human hair. Alternatively, in the case of a flip-chip technique, the pads on the die are no longer restricted to its periphery, but are instead located over the entire face of the die. Irrespective of whether we use a wire bond or flip-chip approach, the package’s substrate itself may be made out of the same material as a printed circuit board, out of ceramic, or out of some even more esoteric material. Another technique to get the most silicon into a small package is to take a die, flip it over, and mount it face down on the package substrate using a flip-chip technique. In the case of Chip- Scale Package (CSP) technology, the package is barely larger than the die itself. In one technique, the chip is flipped over and mounted on an interposer, which is used to redistribute and rearrange the signals. A System-on-Chip (SoC) approach is to create a single humongous die, which is subsequently encased in its own package. In the case of a packaging style known as a Pin Grid Array (PGA), the package’s external connections are arranged as an array of conducting leads, or pins, in the base.