Chapter 2 - Architecture: CPU and Memory

Abstract

This chapter discusses the architecture of the central processing unit (CPU) and the memory of the '430 family. The MSP430 utilizes a 16-bit RISC architecture, which is capable of processing instructions on either bytes or words. The CPU is identical for all members of the '430 family. It consists of a 3-stage instruction pipeline, instruction decoding, a 16-bit ALU, four dedicated-use registers, and twelve working (or scratchpad) registers. The CPU is connected to its memory through two 16-bit busses, one for addressing, and the other for data. All memory, including random access memory (RAM), read only memory (ROM), information memory, special function registers, and peripheral registers are mapped into a single, contiguous address space. This architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains available for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented. And the second reason is because there are plenty of working registers.