Abstract
This chapter discusses multi-valued logic in arithmetic units. Viability and research interest in a new area competing with an established engineering discipline depend upon three factors. Firstly, an intellectual challenge must exist to discover new structures and concepts thereto deemed unlikely. Secondly, if the engineering environment is considered, it is important to establish physical realizability of the proposed structures. Thirdly, one must attempt to answer the question of applicability. New methods would find practical application if it could be shown that they can compete with the existing methodology. The chapter focuses on one such application, namely, that of parallel multipliers. Small and medium-sized computing systems provide a hardware multiplication function by some variation of the “three-register shift and add” technique. The idea is to add the multiplicand to right-shifted versions of the partial products, performing the add whenever the multiplier bit is a one in the binary-weighted position that corresponds to the current shift position. The chapter provides an account of the pros and cons of multi-valued approaches in large arithmetic circuits.
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