Abstract
This chapter also summarizes a number of design considerations and problem areas. It focuses on the basic concepts of design and analysis. These design considerations and problem areas include logic noise in the output signals; problems associated with asynchronous inputs, metastability, and clock distribution; and the initialization and reset of the finite state machine (FSM). Improper design of an FSM can lead to the presence of logic noise in output signals, and this noise can cause the erroneous triggering of a next stage switching device to which the FSM is attached. Therefore, it may be important that FSMs be designed to issue signals that are free of unwanted logic transients (noise) called glitches. There are two main sources of output logic noise in an FSM: glitches produced by state variable race conditions and glitches produced by static hazards in the output logic. A glitch that occurs as a result of two or more state variable changes during a state-to-state transition is called an output race glitch or simply ORG.
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