Chapter 10 - Silicon Virtual Prototyping for FPGAs

Abstract

This chapter presents the concept of silicon virtual prototyping for field programmable gate arrays (FPGAs). It highlights how the silicon virtual prototype (SVP) concept originated in the ASIC world. It also presents some alternative SVP manifestations and the problems associated with those manifestations. Silicon virtual prototyping (SVP) for field programmable gate arrays (FPGA) can be achieved by providing a mixture of floor planning and preplace-and-route timing analysis. This is coupled with the ability to perform place-and-route on individual design blocks that dramatically speeds up the implementation process. This form of SVP commences with a graphical top-down view of the target FPGA device showing all of the internal logical resources, such as look-up tables (LUT), registers, slices, configurable logic blocks (CLB) CLBs, embedded random access memory (RAM), and multipliers. , The SVP generator loads the ensuing hierarchical LUT/CLB-Ievel netlist, along with any associated timing and physical constraints, and automatically creates an initial floor plan. This auto-generated floor plan shows a collection of square and/or rectangular blocks, each of which corresponds to a top-level module in the design. If any of these top-level modules contains submodules, then these are shown as embedded blocks in the floor plan. The various FPGA and EDA vendors provide RTL-level floor-planning tools with varying degrees of sophistication.