Chapter 10 - Post-Partitioning Verification

Abstract

This chapter discusses the verification of the hardware/software (HW/SW) components of the design that result from the earlier partitioning step. The chapter discusses the verification that can and should be performed on the post-partitioned models of the system. This includes the establishment of the types of verification that can be performed and the importance of separating issues, such as functional verification, performance verification, and implementation verification. Post-partitioning verification is introduced into the electronic system-level (ESL) design flow to discover design errors that are introduced before register-transfer level(RTL) and software implementation. Verification at this stage benefits from a reduced abstraction gap between specification and design under verification (DUV). The post-partitioned DUV has no cycle-level timing and the software will be operating on high-level data structures, such as transactions, rather than register-level data. Validation means making sure the specification is correct—that is, the specification captures the product design requirements. Verification means making sure the implementation is correct, ensuring that it conforms to the requirements recorded in the specification.