Channel-Stress Enhancement Characteristics for Scaled pMOSFETs by Using Damascene Gate With Top-Cut Compressive Stress Liner and eSiGe

Abstract

A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 muA/mum at Vds = Vgs = -1.0 V and Ioff = 100 nA/mum is achieved for the damascene-gate pFET with 0.3-mum channel width and 40-nm gate length.