Channel modeling of wireless 3D-chip based on ray-tracing

Abstract

The resource constraints and accuracy requirements for Internet of Things (IoT) memory chips need three-dimensional (3D) monolithic integrated circuits, of which the increasing stack layers (currently more than 176) also cause excessive energy consumption and increasing wire length. In this paper, we propose and describe the channel modeling for wireless 3D chips based on ray-tracing. However, due to the reflection and refraction characteristics in each layer, the complex and diverse wireless paths in 3D chips add great difficulty to the channel characterization. To facilitate the modeling in massive layer wireless 3D chips based on ray-tracing, both boundary-less and boundary-constrained wireless 3D chips models are proposed based on ray-tracing, of which the channel gain can be obtained by a computational efficient approximate algorithm. These wireless 3D models with approximation algorithm can well characterize the wireless 3D chip channel in aspect of complete reflection and refraction characteristics, and avoid massive wired connections, high power consumption of cross-layer communication and high-complexity of 3D chips channel characterization. Numerical results show that: (1) The difference rate between the two models is lower than 0.001% (signal transmit through 20 layers); (2) the channel gain decreases sharply if refract time increases; and (3) the approximate algorithm can achieve an acceptable accuracy (error rate lower than 0.1%).