Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure

Abstract

The growing complexity and size of designs have driven chip implementation teams to adopt hierarchical design methodologies that divide-and-conquer the design closure task. Wherein, the large chip is partitioned into physical blocks with boundary constraints for physical synthesis which are then integrated at the top-level to achieve overall design closure. Each block could be further partitioned until the block sizes are manageable from a tool turnaround time perspective. A key aspect to efficient hierarchical design involves generation of realistic block-level timing budgets and physical constraints (contracts) to enable parallel implementation of each block. In a typical hierarchical design flow, these block-level contracts are created based on early estimations of timing and wiring from the floorplanning phase but evolve as the design progresses, often requiring several iterations of design integration to converge. High-performance designs require efficient contract management while allowing seamless design closure optimizations across levels of hierarchy. This talk will focus on some of the challenges in managing contracts with emphasis on the implications for physical synthesis tools used in hierarchical design closure.