Abstract
Low voltage designs continue to play important roles, as well as creating challenges, in modern analog and mixed-signal integrated circuits (IC) that are expected to operate under low supply voltage. This is either due to the technology scaling into sub-100 nm CMOS, or in the context of low-power battery-operated devices that force the ICs to function less than the nominal supply voltage at the specific technology node [1–13]. Both situations create stringent requirements in analog and mixed-signal IC designs due to low-supply voltage headroom, especially when the supply voltage is lower than the nominal value of that technology, e.g. an analog IC designed in 0.18 μm CMOS must tolerate the reduced voltage headroom of a 1.2 V supply voltage while it cannot benefit from smaller parasitics and higher speed of more advanced CMOS technologies, like 130 or 90 nm.
Published Version
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