Challenges for plasma etch integration of ferroelectric capacitors in FeRAM's and DRAM's

Abstract

The plasma etch process requirements are different for etching 2μm ferroelectric capacitor structures in FeRAM's (SRAM) vs. the smaller capacitor sizes (0.2–0.5 μm) of DRAM's. Plasma etch integration of ferroelectric capacitors presents three major differences between FeRAM's and DRAM's. The first difference is in the ferroelectric capacitor structure. FeRAM's use planar capacitors with top side metal contacts to vias while DRAM's use vertical capacitor structures with bottom side contact to a poly post structure. The second major difference is in material selected and thickness of layers. FeRAM's use thicker electrodes of Pt or Ir and a thicker PZT or Y1 dielectric layer. FeRAM's use a thick bottom electrode (and a thin top electrode) consisting of Pt, Ru or Ir and a thin BST dielectric layer. The third major difference is the plasma etch process requirements for the two devices. FeRAM's require a clean etch process and no corrosion. Profile is not critical but should be maintained at greater than 60° for 2μm bottom post electrode. An HRe− (Highly Density Reflected Electron) etch system is used to develop process trends for ferroelectric capacitor applications.