Challenges and emerging trends of DSP-enabled frequency synthesizers

Abstract

Introduction Frequency synthesizers are pervasively utilized in almost every electronic system for generation of the well-defined clock frequencies of interest. For instance, in the modern wireless transceiver, a phase-locked loop (PLL) is commonly used to generate RF frequencies to up-convert and down-convert the analog signal. On the baseband side, the mixed-signal circuit, such as switched-capacitor filters, as well as digital VLSI also require PLLs to synthesize various clock domains. Moreover, the trend of future electronic design will continue to integrate more functionality, support multiple standards, and multi-channels in a system-on-chip (SoC) platform, which will inevitably increase the number of frequency synthesizers for various analog and digital circuit blocks. As a result, minimizing the power and area consumption of a frequency synthesizer becomes increasingly critical, or it can become the dominant cost factor in the overall system. This system trend has been driving PLL design towards more reconfigurability, wider tuning range and lower cost. The digitally-assisted PLL design concept becomes a natural consequence of this trend, as the flexibility offered via digital means is always appealing. Conventionally, the frequency synthesizer is implemented using an analog approach, i.e., the charge-pump PLL, as shown in Figure 4.1(a). The basic operation of this type of PLL has been well documented in textbooks and the literature [1, 2]. In brief, it processes the phase information in the analog domain via a phase frequency detector and a charge-pump circuit, so that the phase difference turns into current pulses. This current signal is then converted into voltage form via the analog loop filter, which typically consists of capacitor and resistor array. Some degree of digitally-assisted concept was adopted for this type of PLL, mainly to digitally reconfigure the analog loop filter and voltage-controlled oscillator (VCO). For example, the PLL may be required to support different PLL loop bandwidths and/or a wide VCO tuning range. The digitally switched capacitor or resistor bank is a common choice to support this kind of operation. While this analog PLL topology has been widely adopted and proven in both the literature and commercial products, it presents a challenge to scale with technology. The analog loop filter is typically composed of bulky passive components whose values are determined by the desirable PLL loop bandwidth, and cannot be arbitrarily reduced.