Carrier removal and transport in photonic integrated circuit ready InGaAsP/InP substrate: Electrical and transients of charges evaluation

Abstract

InGaAsP based technologies are more favorable due to its unique monolithic integrated nature. For an efficient electro-optical device structure, there is a keen interest to develop active and passive components to suffice the needs of monolithic platform. Thus, carrier's transport and removal regions are carefully fabricated with low optical and electronic signal loss in order to optimize the signal to noise ratio (SNR) to effectively produce monolithic chip. In this specialized study we have provided an insight about the effective multi-implant ion-assisted carrier removal capability of the highly conductive epitaxially grown InGaAsP/InP device matrix as PIC's substrate. For this multi-implant strategy has been adopted with C+ and Ni+ ions implanted separately. Their dosage's along with ion energies are simulated rigorously before the actual implantations. Post implant measurements of Sheet resistance, mobility, drift driven electric fields, current-voltage, Arrhenius based activation energies, charge based transient analysis and detailed investigations of traps have been performed to study the viability of carrier removal scheme for the stable as well as reversible electrical isolation of this photonic integrated circuit's platform.Trap parameters identified as a result of a specialized charge deep level transient spectroscopy provides an insight about the energy levels and possible evaluation of recombination/generation centers for effective photonic activity within the device regions. The optical loss study has been performed to inspect the optical hindrance levels into the said InGaAsP PIC matrix.