Carbon Nanotube Interconnection and Its Electrical Properties for Semiconductor Applications

Abstract

In this work, the integration and its electrical properties of a carbon nanotube (CNT) interconnect for semiconductor applications are presented. A series array of 1000 vias made of vertically grown CNTs was achieved with uniform electrical resistance within the wafer. The integration of CNT interconnection was implemented with conventional semiconductor processes by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning on the wafer. Multi walled CNTs (MWCNTs) as the interconnection, titanium nitride as the bottom electrode, and aluminum with a titanium contact layer as the top electrode were used. We demonstrated well-defined CNT via interconnect with 700 nm via holes on a full-sized wafer. A via resistance of 350 kΩ and a CNT density of 2.7×1010/cm2 were achieved with a small resistance variation within the wafer, which also corresponded to 51.3 kΩ per MWCNT 10 nm in diameter. Possible approaches to further decrease of electrical resistance are suggested.