Carbon co-implantation Used to Improve NMOS Threshold Voltage Roll-off Characteristics Study in 65nm Node CMOS Technology

Abstract

Around 50mV RSCE and SCE improvement has been obtained by C co-implantation optimization in 65nm node CMOS technology. Besides this, gate to source/drain overlap capacitance (Cgd0) and junction capacitance (Cj) are seen to be reduced 6% and 11% respectively. C co-implantation before and after halo implantation are compared also, the result reveals that C co-implantation after halo implantation helps to improve NMOS drain induced barrier lowering (DIBL) features. Gate oxide leakage comparison for different C co-implantation conditions indicates that C co-implantation induces no gate oxide quality degradation.