Capacitor-Less Low-Dropout (LDO) Regulator With 99.99% Current Efficiency Using Active Feedforward and Reverse Nested Miller Compensations

Gwang Sub Kim,Goo-Han Ko,Donghyun Baek,Jae Kyung Park

doi:10.1109/access.2019.2930079

Gwang Sub Kim, Goo-Han Ko + Show 2 more

Open Access

https://doi.org/10.1109/access.2019.2930079

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Abstract

In this paper, an output capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) is implemented. To increase the current efficiency, low quiescent current less than 10 μA is used. The stability problem arising from the low bias current is overcome by applying two kinds of compensation methods. By drawing the pole-zero plot using the open-loop transfer function obtained by the small-signal modeling, the stability of the proposed LDO is guaranteed to be less than 70 mA. By using the proposed compensation methods, two zeros of the right-half plane (RHP) can be placed in the left-half plane (LHP) to prevent lagging and reduce the on-chip compensation capacitor. The current efficiency of the proposed LDO is 99.99% at the load current of 70 mA.

Highlights

The low-dropout (LDO) regulator is an important part of power management integrated chips (PMIC) such as portable devices
PROPOSED LDO DESIGN In this paper, we propose a multistage LDO using an active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) structure (AFF-RNMC)
The right-half plane (RHP) zero generated by Cm1 in the second stage of proposed LDO, since the importance of the current supplied to the output becomes 1 /sCm1 greater than gm2 and the current phase is opposite

Summary

INTRODUCTION

The low-dropout (LDO) regulator is an important part of power management integrated chips (PMIC) such as portable devices. It is challenging to design LDOs with low quiescent currents that have enough gain with a multistage structure, are not subject to load current magnitude from minimum to maximum and satisfy stability requirements. At heavy-load currents, the use of large PTs seems to achieve high efficiency with low dropout voltage, but as the PT size increases, the parasitic capacitor that is present in the transistor reduces the phase margin significantly. Since the second pole moves to the lower frequency and a stability issue occurs, the value Cm1 should be increased to lower the UGBW frequency as well For this reason, both Cm1 and Cm2 are designed to be large in the NMC structure so that a Q value and a phase margin can be secured. The proposed AFF-RNMC LDO has a large real term, which can reduce the size of Cm2 more than NMC or RNMC, reducing the total size of LDO

ANALYSIS OF PROPOSED LDO

MEASUREMENT RESULT

CONCLUSION