Capacitorless 2T-DRAM for Higher Retention Time and Sense Margin

Abstract

This article showcases a junctionless (JL)/ accumulation mode (AM) transistor connected with an access JL transistor-based capacitorless dynamic random access memory (2T-DRAM) cell. The access transistor (AT) is utilized to reduce the leakage and, thus, improves the retention time (RT) and sense margin (SM) of the proposed capacitorless 2T-DRAM cell. Simulation results reveal that the 2T-DRAM cell achieved a maximum SM of $\sim 4.6~\mu \text{A}/\mu \text{m}$ with RT of ~6.5 s for a gate length ( ${L}_{\text {g}}$ ) of 100 nm, almost 100 times against the ITRS prediction for modern DRAM cells. Furthermore, 2T-DRAM shows better gate length scalability with a fixed gate length of AT and achieves RT of ~100 and ~10 ms for a scaled gate length of 10 nm at 27 °C and 85 °C, respectively. The proposed 2T-DRAM cell offers better integration density (scalability) and higher energy efficiency that makes it a potential candidate for artificial intelligence (AI)/Internet-of-Things (IoT) applications.