Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs

Abstract

Aiming to alleviate operational transconductance amplifiers (OTA), this paper describes the design of a capacitive charge pump (CCP) gain-stage for a two-stage pipelined SAR ADCs suitable for low-power sensors. An analog buffer is inevitable to prevent the charge sharing between the capacitive stages. In this work a simple source follower has been used as the analog buffer, showing sufficient linearity and significant power reduction compared to earlier work where a unity-gain OTA was used. To verify the solution, a CCP gain-stage with source follower has been implemented in design of a 14-bit two-stage pipelined SAR ADC in 0.18 µm CMOS. Detailed circuit simulations show that the ADC achieves a SNDR of 83.0 dB while consuming 1.8 µW at a sampling frequency of 10 kHz.