Capacitance–voltage study of single-crystalline Si dots on ultrathin buried SiO2 formed by nanometer-scale local oxidation

Abstract

By applying nanometer-scale local oxidation process to a silicon-on-insulator (SOI) wafer with an ultrathin (2 nm) buried oxide, single-crystalline Si dots were fabricated on the tunnel SiO2, and their electronic properties were studied by capacitance–voltage (C–V) measurements. The C–V curves were primarily interpreted by electron tunneling between the dots and the base substrate. More importantly, the gap states at the dot/SiO2 interface were always observed as a shoulder in the C–V curve. Since such a shoulder was not observed for a simple layered SOI structure, it is strongly suggested that the dot structure inevitably accompanies a large number of the interface gap states, probably due to the undulation of the interface.