Calibration Techniques for the Elimination of Non-Monotonic Errors and the Linearity Improvement of A/D Converters

Abstract

The Analogue/Digital Converters (ADCs) play a very important role in several wideband applications like wired and wireless high speed telecommunication systems (e.g., 802.11g) or communication over powerlines (IEEE P.1901). High definition TV or high precision real time image processing are also examples of applications that require a conversion rate of several hundreds MSamples/sec or even multi-GSsamples/sec. While the ADCs may operate in an optimal way when they are initially designed and verified using DC simulation, a transient simulation can designate several problems that appear during the high speed operation. Additional linearity errors are posed by process variations and component mismatches after the chip fabrication. Finally, operating conditions like voltage supply levels and temperature variations can also affect the linearity of an ADC. Several foreground and background calibration techniques have been proposed in the literature. Most of them are developed for specific ADCs and cannot be applied to different ADC architectures. The most important error sources and the most popular calibration methods for Pipelined, Segmentation/Reassembly and Sigma Delta ADCs as well as a number of generic error compensation methods based on the processing of the ADC output are presented in (Balestrieri et al, 2005). A popular error correction technique used in pipelined ADCs exploits the least significant bit of a “coarse” ADC stage for the error detection and correction. For example, in (Colleran & Abidi, 1993) a 10-bit ADC is constructed by a 4-bit “coarse” and a 7-bit “fine” ADC. The least significant bit of the coarse ADC should match the most significant bit of the fine ADC. Similarly, a 10-bit pipeline ADC consists of a coarse 6-bit and a fine 5-bit ADC in (Sone et al, 1993). Two more recent approaches that are described in (Kurose et al, 2006) and in (Ahmed & Johns, 2005)(Ahmed & Johns, 2008) use 8 stages of 1.5-bit and a 2-bit Flash ADC stage in a 10-bit (or 11-bit in (Ahmed & Johns, 2008)) pipelined ADC architecture. Moreover, in (Ahmed & Johns, 2008), the DAC linearity errors are also taken into consideration. The use of a redundant signed digit also appears at an Analogue-to-Quaternary pipelined converter in (Chan et al, 2006). The ADC architectures that are based on high precision capacitors suffer from the effects of the mismatch. In (Wit et al, 1993), an additional array of capacitors is used for real time