Calibration method for improving the linearity of analog-to-digital converters in CMOS image sensor

Abstract

Random mismatch errors of components in analog-to-digital converters (DACs) degrade the linearity performance of converters realized by these components. A unit capacitor calibration method for improving the linearity of the analog-to-digital converter (ADC) in CMOS image sensor (CIS) is proposed, which improves the static and dynamic performance of the successive approximation register (SAR) ADC by reordering the unit capacitor. Simulation results show that for a 16-bit SAR ADC with the proposed calibration method, the maximum root-mean-square (rms) of integral nonlinearity (INL) and differential nonlinearity (DNL) are enhanced by 66.83% and 60.70% respectively. The mean value of the spurious free dynamic range (SFDR) is improved by 11.37 dB while the mean value of the signal-to-noise-and-distortion ratio (SNDR) is improved by 11.68 dB.