Calibrating simulation tools for nanometer designs

Abstract

Next-generation silicon processes will challenge system-on-a-chip (SOC) designers to increase the accuracy of the data they feed to their high level tools. Minimum circuit features of 250 nm (0.25 μm) or below are demanding. The tools that simulate them will need transistor models and interconnect parameters that reflect nothing less than the actual physical properties of the process in which ICs are to be manufactured. These silicon-calibrated models can then pass their accuracy on to capable transistor-level simulation tools. Silicon calibration calls for for tighter relationships and more effective communication than is now found among silicon foundries electronic design automation (EDA) companies, and IC design groups. The EDA tools must be regularly updated, to equip design engineers to cope with the challenges of nanometer design. Although simulation tools may never predict silicon behavior with 100 percent accuracy, EDA tool vendors and IC fabrication facilities share a responsibility to calibrate their tool suites as closely as possible with actual silicon.