Calculation of on-state I–V characteristics of LDMOSFETs based on an accurate LDD resistance modeling

Abstract

In this paper, we present an I–V model for LDMOSFETs. It is based on modeling the Lightly-Doped Drain (LDD) region of the device as voltage-controlled resistors where velocity saturation effect is also taken into account. Using the LDD region model along with a model for the channel region of the device, the on-state I–V characteristic of the transistor is accurately calculated. The models for the LDD region resistors can be incorporated into a circuit simulator such as HSPICE which has an accurate model for the channel region of the transistor. The accuracy of the models is verified by comparing its results with those of a device simulator. The results show a maximum error of 1% for a wide range of voltages and overlapped LDD region lengths.