Built-in self-test of the Macrolan chip

Abstract

The implementation of self-test in the medium access controller chip for Macrolan, a fibre-optic, local area network, is described. The test style for 80% of the chip's combinational logic is quasiexhaustive testing. This approach, despite its apparent inefficiency in terms of the number of patterns used, gives considerable flexibility to the designer in arranging linear-feedback shift registers and so is easier to implement than some other techniques. The chip also uses a form of random-pattern test, not normally considered for memory testing, instead of a specialized pattern generator. Built-in self-test was implemented without using fault simulation or approximate testability measures. >