Booth folding encoding for high performance squarer circuits

Abstract

Combined Booth encoding and folding techniques are proposed to design squarer circuits using either carry-save or Wallace tree addition techniques. The Booth-folded technique is compared with previous state of the art squarer architectures, showing that a remarkable improvement in timing, power and area performances can be gained both for carry-save and Wallace tree cases. Experimental results, that use built-in-self-test for measuring on chip squarer performance, are presented. The measurements confirm the advantages of the Booth-folded architecture.