Bit significance based reconfigurable approximate restoring dividers and square rooters

Abstract

Approximate computing has received significant recognition for enhancing energy-efficiency in error-resilient applications. This paper proposes bit significance based reconfigurable approximate restoring dividers and square rooters for improved energy-efficiency. Configurable subtractor cells (CSCs) which can function both accurately and approximately are proposed along-with a simplified and scalable overflow detection hardware as major design units. These units are subsequently integrated to form complete divider and square rooter architectures. The CSCs are used to maneuver the input bits based on their progressive significance which affects the accuracy of the design. The proposed approximate designs have the ability to switch between the approximate and accurate operating modes making it suitable for both error-resilient and error-sensitive applications. For 16/8 division the proposed approximate divider reduces energy by 49% with normalized mean error distance of 0.45% when synthesized on CMOS 45-nm technology node. The 16-bit proposed approximate square rooter shows an energy reduction of 36% with marginal accuracy loss. Extensive simulation results of approximate designs are provided and compared with the state-of-the-art approximate designs. The effectiveness of the proposed approximate designs for image processing applications is demonstrated and evaluated.