Abstract
Galois-field multiplication algorithms and their systolic realizations are proposed. Parallel and serial architectures as well as their VLSI implementations are presented. They are based on the standard-basis representation of the Galois-field elements. Our algorithms allow the two operands to enter the systolic arrays in the same order. Only one control signal for the serial systolic array is required as compared to two in the previous design. Our multipliers are more regular and modular, requiring simple control signal, and compact in terms of silicon area; they are well suited to VLSI implementation. Expansion to higher order Galois fields are easier to realize than other multipliers. High throughput rates are achieved due to their systolic array architectures.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: Journal of VLSI signal processing systems for signal, image and video technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.