BIST method of SRAM for network-on-chip

Abstract

Network-on-chip (NoC) is becoming promising communication architecture for the next-generation system on chips. Intellectual property (IP) core is an important part of NoC system, this paper puts SRAM as an IP core to complete the test study of SRAM. We present a Built-in self-test (BIST) method for SRAM of network-on-chip based on reusing network-on-chip as Test Access Mechanism (TAM). The proposed method establishes the functional model of NoC communication architecture and improves March C + algorithm to test SRAM. Reusing NoC as test access mechanism can provide safe and correct data transmission service without extra area overhead. We design it by Verilog language and implement the test in NoC system platform based on Field Programmable Gate Array (FPGA). Experiment results for a NoC system show that the method not only improves fault coverage and the reliability of the test, but also reduces testing time with small increase in area overhead and achieves higher test speed.