Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs

Abstract

We investigated a bipolar transistor with a buried layer formed by high-energy ion implantation without the epitaxitial silicon layer growth. We focused mainly on the reduction of junction leakage current related to implantation damages, which could be achieved by rapid thermal annealing. Consequently, the maximum current gain of 155 and the cutoff frequency of 17.3 GHz were achieved with BV CE0=5.0 V. Moreover, this fabrication process is applicable to the conventional complementary metal oxide semiconductor (CMOS) process with the retrograde twin wells without additional process steps. Therefore, this technique can be very promising for the fabrication of subhalf-micron BiCMOS LSIs.