Abstract
CMOS latchup holding characteristics are experimentally studied for a variety of lateral spacings and initial p- epi layer thicknesses. A transmission line model is used to explain the data and to point out the relationship between the geometric magnitudes and the corresponding holding current and voltage, mainly for shallow epi layers. Additional information regarding carrier transport during latchup and related high-injection effects is obtained from bipolar transistor measurements and analysis. It is concluded that the lateral bipolar is maintained active by carrier flow within the field-implanted region, unless the final epi is significantly thicker than the well depth. The major benefits of shallow epi are, therefore: 1) a shunting distributed path between the field-implanted layer and the heavily doped substrate, and 2) to increase the vertically injected current components that are diverted away from the latchup feedback loop.
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